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| IRFR110, IRFU110 Data Sheet July 1999 File Number 3275.3 4.7A, 100V, 0.540 Ohm, N-Channel Power MOSFETs These are N-Channel enhancement mode silicon gate power field effect transistors designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. These advanced power MOSFETs are designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers and drivers for high-power bipolar switching transistors requiring high speed and low gate-drive power. These transistors can be operated directly from integrated circuits. Formerly developmental type TA17441. Features * 4.7A, 100V * rDS(ON) = 0.540 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information PART NUMBER IRFU110 IRFR110 PACKAGE TO-251AA TO-252AA BRAND IFU110 IFR110 Symbol D NOTE: When ordering, use the entire part number. G S Packaging JEDEC TO-251AA SOURCE DRAIN GATE JEDEC TO-252AA GATE SOURCE DRAIN (FLANGE) DRAIN (FLANGE) 4-371 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRFR110, IRFU110 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRFR110, IRFU110 100 100 4.7 3.3 17 20 30 0.2 19 -55 to 175 300 260 UNITS V V A A A V W W/oC mj oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Rating (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V (Figure 10) VGS = VDS, ID = 250A VDS = Rated BVDSS , VGS = 0V VDS = 0.8 x Rated BVDSS , VGS = 0V, TJ = 150oC MIN 100 2 4.7 1.3 VGS = 10V, ID 5.6A, VDS = 0.8 x Rated BVDSS , RL = 14, IG(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) Measured from the Drain Lead, 6mm (0.25in) from Package to Center of Die Measured from The Source Lead, 6mm (0.25in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S TYP 0.41 2.0 7.6 24 14 14 5.2 1.5 2.2 180 82 15 4.5 MAX 4 25 250 100 0.540 11 36 21 21 7.7 - UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current On-State Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 4) Forward Transconductance (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD VDS > ID(ON) x rDS(ON)MAX , VGS = 10V VGS = 20V ID = 3.3A, VGS = 10V (Figures 8, 9) VDS = 50V, IDS = 3.3A (Figure 12) VDD = 50V, ID 5.6A, RGS = 24, RL = 9.1, VGS = 10V MOSFET Switching Times are Essentially Independent of Operating Temperature - Internal Source Inductance LS - 7.5 - nH Junction to Case Junction to Ambient RJC RJA Free Air Operation - - 5.0 110 oC/W oC/W 4-372 IRFR110, IRFU110 Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 2) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode D MIN - TYP - MAX 4.7 17 UNITS A A G S Source to Drain Diode Voltage (Note 4) Reverse Recovery Time Reverse Recovery Charge NOTES: VSD trr QRR TJ = 25oC, ISD = 4.7A, VGS = 0V (Figure 13) TJ = 25oC, ISD = 5.6A, dISD/dt = 100A/s TJ = 25oC, ISD = 5.6A, dISD/dt = 100A/s 46 0.17 96 0.38 2.5 200 0.83 V ns C 2. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 3. VDD = 25V, starting TJ = 25oC, L = 1.3mH, RG = 25, peak IAS = 4.7A. 4. Pulse test: pulse width 300s, duty cycle 2%. Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 Unless Otherwise Specified 5 ID , DRAIN CURRENT (A) 0 4 3 2 1 0 25 50 75 100 125 150 175 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 10 ZJC , TRANSIENT THERMAL IMPEDANCE 0.5 1 0.2 0.1 0.05 0.1 0.02 0.01 SINGLE PULSE PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC 10-3 10-2 10-1 1 10 0.01 10-5 10-4 t1 , RECTANGULAR PULSE DURATION (s) FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-373 IRFR110, IRFU110 Typical Performance Curves 102 Unless Otherwise Specified (Continued) 10 TC = 25oC TJ = MAX RATED SINGLE PULSE 10s 100s 1ms VGS = 10V ID , DRAIN CURRENT (A) 8 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID , DRAIN CURRENT (A) VGS = 8V 10 6 VGS = 7V 4 VGS = 6V 2 VGS = 5V VGS = 4V 0 10 20 30 40 VDS , DRAIN TO SOURCE VOLTAGE (V) 50 1.0 OPERATION IN THIS AREA LIMITED BY rDS(ON) 0.1 1 10 10ms DC 102 103 0 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS 10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 10 VGS 10V ID , DRAIN CURRENT (A) ID , DRAIN CURRENT (A) 8 VGS 8V 6 VGS 7V 4 VGS = 6V 2 VGS 5V 0 0 2 4 6 VGS 4V 8 10 VDS , DRAIN TO SOURCE VOLTAGE (V) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS 50V 1 TJ = 175oC TJ = 25oC 0.1 10-2 0 2 4 6 8 10 VGS , GATE TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS 5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 3.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V rDS(ON) , DRAIN TO SOURCE 4 ON RESISTANCE () 2.4 3 1.8 ID = 3.3A 2 VGS = 10V 1 VGS = 20V 1.2 0.5 0 0 4 8 12 ID , DRAIN CURRENT (A) 16 20 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 TJ, JUNCTION TEMPERATURE (oC) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 4-374 IRFR110, IRFU110 Typical Performance Curves 1.25 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1.15 C, CAPACITANCE (pF) 400 Unless Otherwise Specified (Continued) 500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS 1.05 300 CISS COSS 100 CRSS 0.95 200 0.85 0.75 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 0 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 102 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 2.5 gfs , TRANSCONDUCTANCE (S) ISD , SOURCE TO DRAIN CURRENT (A) 2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS 50V TJ = 25oC 102 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 10 1.5 TJ = 175oC 1.0 TJ = 175oC 1.0 TJ = 25oC 0.1 0.5 0 0 2 4 6 ID , DRAIN CURRENT (A) 8 10 0 0.4 0.8 1.2 1.6 2.0 VSD , SOURCE TO DRAIN VOLTAGE (V) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS , GATE TO SOURCE VOLTAGE (V) ID = 5.6A 16 VDS = 80V VDS = 50V VDS = 20V 12 8 4 0 0 2 4 6 8 10 Qg, GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-375 IRFR110, IRFU110 Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VDS + tOFF td(OFF) tf 90% 90% RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS 12V BATTERY 0.2F 50k 0.3F G DUT 0 IG(REF) 0 IG CURRENT SAMPLING RESISTOR S VDS ID CURRENT SAMPLING RESISTOR IG(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS 4-376 IRFR110, IRFU110 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-377 |
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